Lead prototype enablement for imec's RISC-V HPC/AI compute systems.
What you will do
Compute System Architecture (CSA) is imec's center of excellence for hardware-software-technology co-design of future compute systems. We work in close collaboration with imec's expertise centers in applications, technology, circuits, and design to innovate and pathfind next-generation compute architectures across AI, HPC, automotive, space, and other domains. CSA operates across six imec centers — Belgium, the Netherlands, Germany, the UK, the USA, and Qatar. This position is based primarily in Leuven, Belgium.
We are looking for an R&D Group Manager to lead the Platform, Prototypes and Physical-Aware Design (P3D) group. You will head a research group focused on enabling novel architectures for future compute systems in the AI, HPC, and automotive domains, with direct ownership of the silicon prototypes that validate CSA's IP and architectural research.
The group is central to enabling imec's CMOS 2.0 architecture vision — the shift beyond monolithic SoCs toward functionally partitioned, 3D-integrated compute systems in which logic, memory, power delivery, and interconnect are co-designed across heterogeneous technology tiers. Realizing CMOS 2.0 in silicon depends on tightly coupling architecture, physical-aware implementation, under one roof. This vision will be enable by architecture technology co-optimization for next-generation HPC and Automotive systems using available foundry technology – that is the P3D group’s mandate.
You are motivated by the opportunity to work within an industrial research startup unit that offers fast growth and high visibility, access to leading-edge silicon technology (beyond 2nm), a team of technical experts from multiple domains committed to true HW-SW co-design, and a highly competitive international environment.
Your responsibilities
- Lead a team composed of Principal SoC Architect, Chiplet Architects, and mid-level R&D engineers working on HW-SW co-design.
- Drive the research and development required to realize the IP developed by the CSA department, from architecture through physical-aware implementation and prototype tape-out.
- Enable the team to generate IP directly from architectural specifications, spanning SystemC (transaction-level/virtual-platform) models and RTL (Verilog), with High-Level Synthesis (HLS) as a key path from algorithmic/behavioral descriptions to synthesizable implementation.
- Provide both technical and operational leadership to the group, fostering cross-team interaction and a culture of innovation.
- Carry out day-to-day line management of the team.
- Conduct quarterly individual reviews with team members and support their career development.
What we do for you
We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.
We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.
We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
Who you are
- At least 10 years of relevant experience in digital system architecture and design.
- A strong understanding of the SoC design and architecture flow.
- Experience in RISC-V-based system architecture.
- At least 2 years of line management experience, ideally leading senior architects alongside mid-level researchers and engineers.
- Hands-on experience with industry-standard EDA tools (Synopsys, Cadence).
- Familiarity with SystemC-based modeling and High-Level Synthesis (HLS) flows (e.g. Catapult, Stratus HLS, Vitis HLS) for IP development from behavioral description to RTL.
- Experience in functional verification at IP and SoC level, including UVM/SystemVerilog and coverage-driven verification methodologies.
- Proficiency with scripting languages for automated design integration flows.
- Excellent written and spoken English, as you will work in a multicultural team and closely with our international partners.
- Strong organizational skills, sound time management, and the ability to prioritize effectively.
- A structured, transparent, and accurate way of working, with a clear appreciation for good documentation.
- A collaborative team player who enjoys sharing knowledge and experience with colleagues.
- Networking skills, creativity, persistence, and genuine passion for the domain.
Considered an asset:
- Experience with die-to-die interfaces and protocols (e.g. UCIe) for high-performance data exchange between chiplets.
- Experience designing automation scripts for design and verification flows.
